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1 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram 8 meg x 8 edo dram part numbers refresh part number addressing package refresh mt4lc8m8c2dj-x 4k soj standard mt4lc8m8c2dj-x s 4k soj self mt4lc8m8c2tg-x 4k tsop standard mt4lc8m8c2tg-x s 4k tsop self mt4lc8m8p4dj-x 8k soj standard mt4lc8m8p4dj-x s 8k soj self mt4lc8m8p4tg-x 8k tsop standard mt4lc8m8p4tg-x s 8k tsop self x = speed features ? single +3.3v 0.3v power supply ? industry-standard x8 pinout, timing, functions, and packages ? 12 row, 11 column addresses (c2) or 13 row, 10 column addresses (p4) ? high-performance cmos silicon-gate process ? all inputs, outputs and clocks are lvttl- compatible ? extended data-out (edo) page mode access ? 4,096-cycle cas#-before-ras# (cbr) refresh distributed across 64ms ? optional self refresh (s) for low-power data retention options marking ? refresh addressing 4,096 (4k) rows c2 8,192 (8k) rows p4 ? plastic packages 32-pin soj (400 mil) dj 32-pin tsop (400 mil) tg ? timing 50ns access -5 60ns access -6 ? refresh rates standard refresh (64ms period) none self refresh (128ms period) s* note: 1. the 8 meg x 8 edo dram base number differentiates the offerings in one place mt4lc8m8 c2. the fifth field distinguishes the address offerings: c2 designates 4k addresses and p4 designates 8k addresses. 2. the # symbol indicates signal is active low. *contact factory for availability part number example: mt4lc8m8c2dj-5 dram mt4lc8m8p4, mt4lc8m8c2 for the latest data sheet, please refer to the micron web site: www.micronsemi.com/mti/msp/html/datasheet.html pin assignment (top view) key timing parameters speed t rc t rac t pc t aa t cac t cas -5 84ns 50ns 20ns 25ns 13ns 8ns -6 104ns 60ns 25ns 30ns 15ns 10ns **nc on c2 version and a12 on p4 version 32-pin soj 32-pin tsop v cc dq0 dq1 dq2 dq3 nc v cc we# ras# a0 a1 a2 a3 a4 a5 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v ss dq7 dq6 dq5 dq4 vss cas# oe# nc / a12 ** a11 a10 a9 a8 a7 a6 v ss v cc dq0 dq1 dq2 dq3 nc v cc we# ras# a0 a1 a2 a3 a4 a5 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v ss dq7 dq6 dq5 dq4 v ss cas# oe# nc/ a12 ** a11 a10 a9 a8 a7 a6 v ss general description the 8 meg x 8 dram is a high-speed cmos, dy- namic random-access memory devices containing 67,108,864 bits and designed to operate from 3v to 3.6v. the mt4lc8m8c2 and mt4lc8m8p4 are func- tionally organized as 8,388,608 locations containing eight bits each. the 8,388,608 memory locations are arranged in 4,096 rows by 2,048 columns on the c2 version and 8,192 rows by 1,024 columns on the p4 version. during read or write cycles, each location is
2 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram functional block diagram mt4lc8m8p4 (13 row addresses) a0- a12 ras# 13 13 10 no. 2 clock generator refresh controller no. 1 clock generator v dd v ss 13 we# cas# 10 control logic column- address buffer(10) row- address buffers (13) 8,192 1,024 column decoder oe# dq0- dq7 8 8 8 8 refresh counter row select row decoder sense amplifiers i/o gating data-out buffer data-in buffer 8,192 x 1,024 x 8 memory array complement select 1,024 x 8 8,192 x 8 functional block diagram mt4lc8m8c2 (12 row addresses) a0- a11 ras# 12 12 11 no. 2 clock generator refresh controller no. 1 clock generator v dd v ss 12 we# cas# 11 control logic column- address buffer(11) row- address buffers (12) 4,096 2,048 column decoder oe# dq0- dq7 8 8 8 8 refresh counter row select row decoder sense amplifiers i/o gating data-out buffer data-in buffer 4,096 x 2,048 x 8 memory array complement select 2,048 x 8 4,096 x 8
3 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram uniquely addressed via the address bits. first, the row address is latched by the ras# signal, then the column address is latched by cas#. both devices provide edo- page-mode operation, allowing for fast successive data operations (read, write, or read-modify- write) within a given row. the 8 meg x 8 dram must be refreshed periodically in order to retain stored data. dram access each location in the dram is uniquely addressable, as mentioned in the general description. the data for each location is accessed via the eight i/o pins (dq0- dq7). a logic high on we# dictates read mode, while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we# or cas#, whichever occurs last. an early write occurs when we# is taken low prior to cas# falling. a late write or read-modify-write occurs when we# falls after cas# is taken low. during early write cycles, the data outputs (q) will remain high-z, regardless of the state of oe#. during late write or read-modify-write cycles, oe# must be taken high to disable the data outputs prior to apply- ing input data. if a late write or read-modify- write is attempted while keeping oe# low, no write will occur, and the data outputs will drive read data from the accessed location. figure 1 oe# control of dqs edo page mode dram read cycles have traditionally turned the output buffers off (high-z) with the rising edge of cas#. if cas# went high and oe# was low (active), the output buffers would be disabled. the 8 meg x 8 dram offers an accelerated page mode cycle by elimi- nating output disable from cas# high. this option is called edo, and it allows cas# precharge time ( t cp) to occur without the output data going invalid (see read and edo-page-mode read waveforms in the noted appendix). edo operates like any dram read or fast-page- mode read, except data is held valid after cas# goes high, as long as ras# and oe# are held low and we# is held high. oe# can be brought low or high while cas# and ras# are low, and the dqs will transition between valid data and high-z. using oe#, there are two methods to disable the outputs and keep them disabled during the cas# high time. the first method is to have oe# high when cas# transitions high and keep oe# high for t oehc thereafter. this will disable the dqs, and they will remain disabled (regardless of the state of oe# after that point) until cas# falls again. the second method is to have oe# low when cas# transitions high and then bring oe# high for a minimum of t oep anytime during the cas# high period. this will disable the dqs, and they will remain disabled (regardless of the state of oe# after that point) until cas# falls again (see figure 1). during v v ih il cas# v v ih il ras# v v ih il addr row column (a) column (b) dont care undefined v v ih il oe# v v ioh iol open dq t od valid data (b) valid data (a) column (c) valid data (a) t oe valid data (c) column (d) valid data (d) t od t oehc t od t oep t oes the dqs go back to low-z if t oes is met. the dqs remain high-z until the next cas# cycle if t oehc is met. the dqs remain high-z until the next cas# cycle if t oep is met. general description (continued)
4 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram covers all rows. the cbr refresh cycle will invoke the internal refresh counter for automatic ras# address- ing. alternatively, ras#-only refresh capability is inherently provided. however, with this method, some compatibility issues may become apparent. for ex- ample, both c2 and p4 versions require 4,096 cbr refresh cycles, yet each requires a different number of ras#-only refresh cycles (c2 = 4,096 and p4 = 8,192). jedec strongly recommends the use of cbr refresh for this device. an optional self refresh mode is also available on the s version. the self refresh feature is initiated by performing a cbr refresh cycle and holding ras# low for the specified t rass. the s option allows for an extended period of 128ms, or 31.25s per row for a 4k refresh and 15.625s per row for an 8k refresh, when using a distributed cbr refresh. this refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. the self refresh mode is terminated by driving ras# high for a minimum time of t rps. this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras# low-to-high transition. if the dram controller uses a distributed cbr refresh sequence, a burst refresh is not required upon exiting self refresh. however, if the dram controller utilizes a ras#-only or burst cbr refresh sequence, all 1,024 rows must be refreshed using a minimum t rc refresh rate prior to resuming normal operation. edo page mode (continued) other cycles, the outputs are disabled at t off time after ras# and cas# are high or at t whz after we# transi- tions low. the t off time is referenced from the rising edge of ras# or cas#, whichever occurs last. we# can also perform the function of disabling the output drivers under certain conditions, as shown in figure 2. edo-page-mode operations are always initiated with a row address strobed in by the ras# signal, followed by a column address strobed in by cas#, just like for single location accesses. however, subse- quent column locations within the row may then be accessed at the page mode cycle time. this is accom- plished by cycling cas# while holding ras# low and entering new column addresses with each cas# cycle. returning ras# high terminates the edo-page-mode operation. dram refresh the supply voltage must be maintained at the speci- fied levels, and the refresh requirements must be met in order to retain stored data in the dram. the refresh requirements are met by refreshing all 8,192 rows (p4) or all 4,096 rows (c2) in the dram array at least once every 64ms. the recommended procedure is to execute 4,096 cbr refresh cycles, either uniformly spaced or grouped in bursts, every 64ms. the mt4lc8m8p4 in- ternally refreshes two rows for every cbr cycle, whereas the mt4lc8m8c2 refreshes one row for every cbr cycle. so with either device, executing 4,096 cbr cycles v v ih il cas# v v ih il ras# v v ih il addr row column (a) dont care undefined v v ih il we# v v ioh iol open dq t wpz the dqs go to high-z if we# falls and, if t wpz is met, will remain high-z until cas# goes low with we# high (i.e., until a read cycle is initiated). v v ih il oe# valid data (b) t whz we# may be used to disable the dqs to prepare for input data in an early write cycle. the dqs will remain high-z until cas# goes low with we# high (i.e., until a read cycle is initiated). t whz column (d) valid data (a) column (b) column (c) input data (c) figure 2 we# control of dqs
5 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram absolute maximum ratings* voltage on v cc relative to v ss ................ -1v to +4.6v voltage on nc, inputs or i/o pins relative to v ss ....................................... -1v to +4.6v operating temperature, t a (ambient) ... 0c to +70c storage temperature (plastic) ............ -55c to +150c power dissipation ................................................... 1w *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (note: 1) (v cc = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v cc 3 3.6 v input high voltage: valid logic 1; all inputs, i/os and any nc v ih 2v cc + 0.3 v 26 input low voltage: valid logic 0; all inputs, i/os and any nc v il -0.3 0.8 v 26 input leakage current: any input at v in (0v v in v cc + 0.3v) ; i i -2 2 a 27 all other pins not under test = 0v output high voltage: i out = -2ma v oh 2.4Cv output low voltage: i out = 2ma v ol C 0.4 v output leakage current: any output at v out (0v v out v cc + 0.3v); i oz -5 5 a dq is disabled and in high-z state
6 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram i cc operating conditions and maximum limits (notes: 1, 2, 3, 5, 6) (v cc = +3.3v 0.3v) 4k 8k parameter/condition symbol speed refresh refresh units notes standby current: ttl i cc 1 all 1 1 ma (ras# = cas# = v ih ) standby current: cmos (ras# = cas# ? v cc - 0.2v; dqs may be left open; i cc 2 all 500 500 a other inputs: v in ? v cc - 0.2v or v in 0.2v) operating current: random read/write i cc 3 -5 175 135 ma 25 average power supply current -6 165 125 (ras#, cas#, address cycling: t rc = t rc [min]) operating current: edo page mode i cc 4 -5 155 155 ma 25 average power supply current -6 125 125 (ras# = v il , cas#, address cycling: t pc = t pc [min]) refresh current: ras#-only i cc 5 -5 175 135 ma 22 average power supply current -6 165 125 (ras# cycling, cas# = v ih : t rc = t rc [min]) refresh current: cbr i cc 6 -5 165 165 ma 4, 7 average power supply current -6 155 155 (ras#, cas#, address cycling: t rc = t rc [min]) refresh current: extended (s version only) average power supply current: cas# = 0.2v or cbr i cc 7 all 400 400 a 4, 7 cycling; ras# = t ras (min); we# = v cc - 0.2v; a0-a11, oe# and d in = v cc - 0.2v or 0.2v (d in may be left open) refresh current: self (s version only) average power supply current: cbr with i cc 8 all 350 400 a 4, 7 ras# ? t rass (min) and cas# held low; we# = v cc - 0.2v; a0-a11, oe# and d in = v cc - 0.2v or 0.2v (d in may be left open)
7 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram ac electrical characteristics (notes: 5, 6, 7, 8, 9, 10, 11, 12) (v cc = +3.3v 0.3v) ac characteristics -5 -6 parameter symbol min max min max units notes access time from column address t aa 25 30 ns column-address setup to cas# precharge t ach 12 15 ns column-address hold time (referenced to ras#) t ar 38 45 ns column-address setup time t asc 0 0 ns row-address setup time t asr 0 0 ns column address to we# delay time t awd 42 49 ns 18 access time from cas# t cac 13 15 ns column-address hold time t cah 8 10 ns cas# pulse width t cas 8 10,000 10 10,000 ns cas# low to dont care during self refresh t chd 15 15 ns cas# hold time (cbr refresh) t chr 8 10 ns 4 cas# to output in low-z t clz 0 0 ns data output hold after cas# low t coh 3 3 ns cas# precharge time t cp 8 10 ns 13 access time from cas# precharge t cpa 28 35 ns cas# to ras# precharge time t crp 5 5 ns cas# hold time t csh 38 45 ns cas# setup time (cbr refresh) t csr 5 5 ns 4 cas# to we# delay time t cwd 28 35 ns 18 write command to cas# lead time t cwl 8 10 ns data-in hold time t dh 8 10 ns 19 data-in setup time t ds 0 0 ns 19 output disable t od 0 12 0 15 ns 23, 24 output enable time t oe 12 15 ns 20 oe# hold time from we# during t oeh 8 10 ns 24 read-modify-write cycle oe# high hold time from cas# high t oehc 5 10 ns oe# high pulse width t oep 5 5 ns oe# low to cas# high setup time t oes 4 5 ns output buffer turn-off delay t off 0 12 0 15 ns 17, 23 capacitance (note: 2) parameter symbol max units input capacitance: address pins c i 1 5pf input capacitance: ras#, cas#, we#, oe# c i 2 7pf input/output capacitance: dq c io 7pf
8 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram ac electrical characteristics (notes: 5, 6, 7, 8, 9, 10, 11, 12) (v cc = +3.3v 0.3v) ac characteristics -5 -6 parameter symbol min max min max units notes oe# setup prior to ras# during hidden refresh cycle t ord 0 0 ns edo-page-mode read or write cycle time t pc 20 25 ns edo-page-mode read-write cycle time t prwc 47 56 ns access time from ras# t rac 50 60 ns ras# to column-address delay time t rad 9 12 ns 15 row-address hold time t rah 9 10 ns ras# pulse width t ras 50 10,000 60 10,000 ns ras# pulse width (edo page mode) t rasp 50 125,000 60 125,000 ns ras# pulse width during self refresh t rass 100 100 s random read or write cycle time t rc 84 104 ns ras# to cas# delay time t rcd 11 14 ns 14 read command hold time (referenced to cas#) t rch 0 0 ns 16 read command setup time t rcs 0 0 ns refresh period t ref 64 64 ms 23 refresh period (2,048 cycles) s version t ref 128 128 ms ras# precharge time t rp 30 40 ns ras# to cas# precharge time t rpc 5 5 ns ras# precharge time exiting self refresh t rps 90 105 ns read command hold time (referenced to ras#) t rrh 0 0 ns 16 ras# hold time t rsh 13 15 ns read-write cycle time t rwc 116 140 ns ras# to we# delay time t rwd 67 79 ns 18 write command to ras# lead time t rwl 13 15 ns transition time (rise or fall) t t250250ns write command hold time t wch 8 10 ns write command hold time (referenced to ras#) t wcr 38 45 ns we# command setup time t wcs 0 0 ns 18 we# to outputs in high-z t whz 12 15 ns write command pulse width t wp 5 5 ns we# pulse widths to disable outputs t wpz 10 10 ns we# hold time (cbr refresh) t wrh 8 10 ns we# setup time (cbr refresh) t wrp 8 10 ns
9 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v cc = +3.3v; f = 1 mhz; t a = 25c. 3. i cc is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. an initial pause of 100s is required after power- up, followed by eight ras# refresh cycles (ras#- only or cbr with we# high), before proper device operation is ensured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 2.5ns. 8. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 9. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 10. if cas# and ras# = v ih , data output is high-z. 11. if cas# = v il , data output may contain data from the last valid read cycle. 12. measured with a load equivalent to two ttl gates and 100pf; and v ol = 0.8v and v oh = 2v. 13. if cas# is low at the falling edge of ras#, output data will be maintained from the previous cycle. to initiate a new cycle and clear the data- out buffer, cas# must be pulsed high for t cp. 14. the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa ( t rac and t cac no longer applied). with or without the t rad (max) limit, t aa, t rac, and t cac must always be met. 15. the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac ( t rac [min] no longer applied). with or without the t rcd limit, t aa and t cac must always be met. 16. either t rch or t rrh must be satisfied for a read cycle. 17. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 18. t wcs, t rwd, t awd, and t cwd are not restrictive operating parameters. t wcs applies to early write cycles. if t wcs > t wcs min, the cycle is an early write cycle and the data output will remain an open circuit throughout the entire cycle. t rwd, t awd and t cwd define read- modify-write cycles. meeting these limits allows for reading and disabling output data and then applying input data. oe# held high and we# taken low after cas# goes low results in a late write (oe#-controlled) cycle. t wcs, t rwd, t cwd and t awd are not applicable in a late write cycle. 19. these parameters are referenced to cas# leading edge in early write cycles and we# leading edge in late write or read-modify-write cycles. 20. if oe# is tied permanently low, late write or read-modify-write operations are not possible. 21. a hidden refresh may also be performed after a write cycle. in this case, we# is low and oe# is high. 22. ras#-only refresh requires that all rows be refreshed at least once every 64ms (4,096 rows for the c2 version and 8,192 rows for the p4 version). cbr refresh requires that at least 4,096 cycles be completed every 64ms. 23. the dqs open during read cycles once t od or t off occur. if cas# stays low while oe# is brought high, the dqs will open. if oe# is brought back low (cas# still low), the dqs will provide the previously read data. 24. late write and read-modify-write cycles must have both t od and t oeh met (oe# high during write cycle) in order to ensure that the output buffers will be open during the write cycle. if oe# is taken back low while cas# remains low, the dqs will remain open. 25. column address changed once each cycle. 26. v ih overshoot: v ih (max) = v cc + 2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. 27. nc pins are assumed to be left floating and are not tested for leakage.
10 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram read cycle t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column cas# we# note 1 t ach dont care undefined note: 1. t off is referenced from rising edge of ras# or cas#, whichever occurs last. -5 -6 symbol min max min max units t off 0 12 0 15 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t rcd 11 14 ns t rch 0 0 ns t rcs 0 0 ns t rp 30 40 ns t rrh 0 0 ns t rsh 13 15 ns timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t crp 5 5 ns t csh 38 45 ns t od 0 12 0 15 ns t oe 12 15 ns
11 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram early write cycle dont care undefined v v ih il valid data row column row t ds t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t dh we# cas# t ach -5 -6 symbol min max min max units t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t rcd 11 14 ns t rp 30 40 ns t rsh 13 15 ns t rwl 13 15 ns t wch 8 10 ns t wcr 38 45 ns t wcs 0 0 ns t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t crp 5 5 ns t csh 38 45 ns t cwl 8 15 ns t dh 8 10 ns t ds 0 0 ns t rad 9 12 ns
12 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram read write cycle (late write and read-modify-write cycles) valid d out valid d in row column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe# t oeh we# t ach cas# dont care undefined -5 -6 symbol min max min max units t od 0 12 0 15 ns t oe 12 15 ns t oeh 8 10 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rcd 11 14 ns t rcs 0 0 ns t rp 30 40 ns t rsh 13 15 ns t rwc 116 140 ns t rwd 67 79 ns t rwl 13 15 ns t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t awd 42 49 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t crp 5 5 ns t csh 38 45 ns t cwd 28 35 ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns
13 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram edo-page-mode read cycle valid data valid data valid data column column column row row dont care undefined t od t cah t asc t cp t rsh t cp t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rrh t rch t off t cac t cpa t aa t clz t cac t cpa t aa t cac t rac t aa t clz t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v oh ol v v ih il ras# oe# t cas t cas cas# we# t coh t oep t oehc t oes t oes t ach t ach t ach -5 -6 symbol min max min max units t oehc 5 10 ns t oep 5 5 ns t oes 4 5 ns t off 0 12 0 15 ns t pc 20 25 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t rcd 11 14 ns t rch 0 0 ns t rcs 0 0 ns t rp 30 40 ns t rrh 0 0 ns t rsh 13 15 ns timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t coh 3 3 ns t cp 8 10 ns t cpa 28 35 ns t crp 5 5 ns t csh 38 45 ns t od 0 12 0 15 ns t oe 12 15 ns
14 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram edo-page-mode early write cycle t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t cah t asc t cah t asc t rah t asr t rad t ach t ach t ach t ar column column column row row t cp t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp v v ih il cas# v v ih il addr v v ih il we# v v ih il dq v v ioh iol ras# dont care undefined t pc 20 25 ns t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t rcd 11 14 ns t rp 30 40 ns t rsh 13 15 ns t rwl 13 15 ns t wch 8 10 ns t wcr 38 45 ns t wcs 0 0 ns t wp 5 5 ns -5 -6 symbol min max min max units timing parameters -5 -6 symbol min max min max units t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t cp 8 10 ns t crp 5 5 ns t csh 38 45 ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns
15 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram edo-page-mode read-write cycle (late write and read-modify-write cycles) dont care undefined t oe t oe t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t cp t cas t rsh t cp t rp t rasp t cas t cp t cas t rcd t csh t pc t crp row column column column row v v ih il cas# v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# we# t prwc t oeh t od t od t od note 1 note: 1. t pc is for late write cycles only. t od 0 12 0 15 ns t oe 12 15 ns t oeh 8 12 ns t pc 20 25 ns t prwc 47 56 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t rcd 11 14 ns t rcs 0 0 ns t rp 30 40 ns t rsh 13 15 ns t rwd 67 79 ns t rwl 13 15 ns t wp 5 5 ns -5 -6 symbol min max min max units timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t awd 42 49 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t cp 8 10 ns t cpa 28 35 ns t crp 5 5 ns t csh 38 45 ns t cwd 28 35 ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns
16 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram edo-page-mode read early write cycle (pseudo read-modify-write) v v ih il v v ih il ras# v v ih il addr v v ih il we# t rasp t rp row column (a) column (n) row v v ih il oe# v v ioh iol t crp t csh t cas t rcd t asr t rah t rad t asc t ar t cah t asc t cah t asc t cah t cp t rsh valid data in t rcs t rch t wcs t oe valid data (b) valid data (a) t whz t cac t cpa t aa t cac t aa open dq t pc rac t t coh t wch t ds t dh t pc column (b) t ach cas# t cas t cas t cp t cp dont care undefined -5 -6 symbol min max min max units t oe 12 15 ns t pc 20 25 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t rcd 11 14 ns t rch 0 0 ns t rcs 0 0 ns t rp 30 40 ns t rsh 13 15 ns t wch 8 10 ns t wcs 0 0 ns t whz 0 12 0 15 ns timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t coh 3 3 ns t cp 8 10 ns t cpa 28 35 ns t crp 5 5 ns t csh 38 45 ns t dh 8 10 ns t ds 0 0 ns
17 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram read cycle (with we#-controlled disable) t clz t cac t rac t aa valid data open t rch t rcs t asc t rah t rad t ar t cah t rcd t cas t csh t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column we# t whz t wpz t cp t asc t rcs column t clz dont care undefined cas# -5 -6 symbol min max min max units timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t cp 8 10 ns t crp 5 5 ns t csh 38 45 ns t od 0 12 0 15 ns t oe 12 15 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t rcd 11 14 ns t rch 0 0 ns t rcs 0 0 ns t whz 12 15 ns t wpz 10 10 ns
18 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram ras#-only refresh cycle (oe# and we# = dont care) row v v ih il cas# v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open dq v v oh ol t rpc cbr refresh cycle (addresses and oe# = dont care) t rp v v ih il ras# t ras note 1 open t chr t csr v v ih il v v oh ol cas# dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh we# t wrp t wrh dont care undefined timing parameters -5 -6 symbol min max min max units t asr 0 0 ns t chr 8 10 ns t cp 8 10 ns t crp 5 5 ns t csr 5 5 ns t rah 9 10 ns -5 -6 symbol min max min max units t ras 50 10,000 60 10,000 ns t rc 84 104 ns t rp 30 40 ns t rpc 5 5 ns t wrh 8 10 ns t wrp 8 10 ns note: 1. end of first cbr refresh cycle.
19 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cac 13 15 ns t cah 8 10 ns t chr 8 10 ns t clz 0 0 ns t crp 5 5 ns t od 0 12 0 15 ns hidden refresh cycle 1 (we# = high; oe# = low) dont care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t crp t rcd t rsh t ras t rp t chr t ras dq v v oh ol v v ih il addr v v ih il v v ih il ras# v v ih il t oe t od oe# t ord cas# -5 -6 symbol min max min max units t oe 12 15 ns t off 0 12 0 15 ns t ord 0 0 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rcd 11 14 ns t rp 30 40 ns t rsh 13 15 ns note: 1. a hidden refresh may also be performed after a write cycle. in this case, we# is low and oe# is high.
20 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram self refresh cycle (addresses and oe# = dont care) v v ih il ras# t rass open v v ih il v v oh ol dq t rpc t chd t rps t rpc t rp t cp cas# we# v v ih il t wrh t wrp t wrh t wrp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) note 1 t csr dont care undefined t cp note 2 ( ) ( ) ( ) ( ) note: 1. once t rass (min) is met and ras# remains low, the dram will enter self refresh mode. 2. once t rps is satisfied, a complete burst of all rows should be executed if ras#-only or burst cbr refresh -5 -6 symbol min max min max units t rpc 5 5 ns t rps 90 105 ns t wrh 8 10 ns t wrp 8 10 ns timing parameters -5 -6 symbol min max min max units t chd 15 15 ns t cp 8 10 ns t csr 5 5 ns t rass 100 100 s t rp 30 40 ns
21 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram 32-pin plastic soj (400 mil) .435 (11.05) .360 (9.14) .750 (19.05) typ .829 (21.05) seating plane .040 (1.02) .380 (9.65) .080 (2.03) .095 (2.42) .145 (3.68) .132 (3.35) .015 (0.38) .020 (0.51) pin #1 id .050 (1.27) typ .445 (11.31) .823 (20.90) .405 (10.29) .399 (10.13) .030 (0.77) r .032 (0.82) .037 (0.95) max dambar protrusion .026 (0.67) .024 (0.61) .030 (0.76) min note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
22 8 meg x 8 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d20_2.p65 C rev. 5/00 ?2000, micron technology, inc. 8 meg x 8 edo dram 32-pin plastic tsop (400 mil) 0.10 +0.10 -0.05 11.76 0.10 1.20 max 0.50 0.10 gage plane 0.25 see detail a 0.10 0.15 +0.03 -0.02 20.96 0.08 pin 1 id detail a 0.95 10.16 0.08 0.43 +0.07 -0.13 0.80 typ 1.27 typ note: 1. all dimensions in millimeters max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.

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